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Staff Profile- Suhardi

suhardi

ASIC Hardware Engineer

Suhardi Tjoa, B.Digital System(Hons), Master of IT(Research)
Phone +61 (3) 99053631 Email : Suhardi.Tjoa@sci.monash.edu.au

ENGINEERING INTERESTS
Suhardi is a detector system development engineer who specialises in the design of ASICs for high speed pixel detector systems for synchroton radiation applications. Specific areas of interest include Real Time DSP, Field Programmable Gate Arrays (FPGAs), Mixed-Circuit design, and programmable System on Chip (SOC) developments.

Previous Development projects have included : 

  • The design and development of a Delta Sigma Analog-to-Digital Converter
  • The analysis and improvement of a signature recognition system 
  • The design of a driver for brushless servo motors

Current Development projects include :

  • Development of a preamplifier for a pixel detector system, initially targeted for solid-state detectors, with small die size and low power consumption.
  • Optimization of the preamp to compensate for pulse pile-up efffects.

Publications

S. Tjoa, An Implementation of Sigma-Delta Analog-to-Digital Converters with Application to Ultrasonic Beamforming, Thesis of Master of IT, Monash Clayton, 2004.